An Algebraic Model for the Analysis of Logical Circuits
IEEE Transactions on Computers
A Heuristic Algorithm for the Testing of Asynchronous Circuits
IEEE Transactions on Computers
Hazard detection in combinational and sequential switching circuits
IBM Journal of Research and Development
Uncertainty, Energy, and Multiple-Valued Logics
IEEE Transactions on Computers
Synchronous Test Generation Model for Asynchronous Circuits
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Fault-Tolerant Computing: A Introduction
IEEE Transactions on Computers
Computational complexity in logic testing
INES'10 Proceedings of the 14th international conference on Intelligent engineering systems
Delay test generation 2: algebra and algorithms
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Accurate QBF-based test pattern generation in presence of unknown values
Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 14.99 |
A nine-valued circuit model for test generation is introduced which takes care of multiple and repeated effects of a fault in sequential circuits. Using this model test sequences can be determined which allow multiple and repeated effects of faults on the internal state of a sequential circuit. Thus valid test sequences are derived where other known procedures, like the D-algorithm, do not find any test although one exists.