Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Symbolic Simulation with Approximate Values
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Conflict driven learning in a quantified Boolean Satisfiability solver
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Testing, Verification, and Diagnosis in the Presence of Unknowns
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
An Exact Solution to the Minimum Size Test Pattern Problem
ICCD '98 Proceedings of the International Conference on Computer Design
Symbolic implication in test generation
EURO-DAC '91 Proceedings of the conference on European design automation
A Nine-Valued Circuit Model for Test Generation
IEEE Transactions on Computers
On the Acceleration of Test Generation Algorithms
IEEE Transactions on Computers
Diagnosis of automata failures: a calculus and a method
IBM Journal of Research and Development
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On Determining the Real Output Xs by SAT-Based Reasoning
ATS '10 Proceedings of the 2010 19th IEEE Asian Test Symposium
SAT'04 Proceedings of the 7th international conference on Theory and Applications of Satisfiability Testing
sQueezeBF: an effective preprocessor for QBFs based on equivalence reasoning
SAT'10 Proceedings of the 13th international conference on Theory and Applications of Satisfiability Testing
Combinational test generation using satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test pattern generation using Boolean satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hi-index | 0.00 |
Unknown (X) values may emerge during the design process as well as during system operation and test application. Sources of X-values are for example black boxes, clock-domain boundaries, analog-to-digital converters, or uncontrolled or uninitialized sequential elements. To compute a detecting pattern for a given stuck-at fault, well defined logic values are required both for fault activation as well as for fault effect propagation to observing outputs. In presence of X-values, classical test generation algorithms, based on topological algorithms or formal Boolean satisfiability (SAT) or BDD-based reasoning, may fail to generate testing patterns or to prove faults untestable. This work proposes the first efficient stuck-at fault ATPG algorithm able to prove testability or untestability of faults in presence of X-values. It overcomes the principal inaccuracy and pessimism of classical algorithms when X-values are considered. This accuracy is achieved by mapping the test generation problem to an instance of quantified Boolean formula (QBF) satisfiability. The resulting fault coverage improvement is shown by experimental results on ISCAS benchmark and larger industrial circuits.