ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Efficient use of large don't cares in high-level and logic synthesis
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A two-state methodology for RTL logic simulation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
The coming of age of (academic) global routing
Proceedings of the 2008 international symposium on Physical design
Ad-Hoc Translations to Close Verilog Semantics Gap
DDECS '08 Proceedings of the 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
Proceedings of the 46th Annual Design Automation Conference
Increasing the accuracy of SAT-based debugging
Proceedings of the Conference on Design, Automation and Test in Europe
Accurate QBF-based test pattern generation in presence of unknown values
Proceedings of the Conference on Design, Automation and Test in Europe
Hi-index | 0.03 |
Don't-care conditions are utilized by many synthesis tools because such conditions provide additional flexibility for logic optimization. However, most techniques only focus on the gate level because it is difficult to handle such conditions accurately at behavior and register transfer levels. This is problematic since the trend is to move toward high-level synthesis. In this paper, we propose innovative methods to handle such conditions accurately at high-level designs. In addition, we propose three novel algorithms based on our new methods to minimize the number of registers that need to be initialized, which can reduce the routing resources used by the reset signals and alleviate the routing problem. We applied our techniques to a five-stage pipelined processor and successfully reduced the number of control registers that need to be initialized by 53%, demonstrating the effectiveness of our approach.