Algorithms for solving Boolean satisfiability in combinational circuits
DATE '99 Proceedings of the conference on Design, automation and test in Europe
On using satisfiability-based pruning techniques in covering algorithms
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Satisfiability-Based Algorithms for Boolean Optimization
Annals of Mathematics and Artificial Intelligence
Accurate QBF-based test pattern generation in presence of unknown values
Proceedings of the Conference on Design, Automation and Test in Europe
LFSR seed computation and reduction using SMT-based fault-chaining
Proceedings of the Conference on Design, Automation and Test in Europe
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This paper addresses the problem of test pattern generation for single stuck-at faults in combinational circuits, under the additional constraint that the number of specified primary input assignments is minimized. This problem has different applications in testing, including the identification of don't care conditions to be used in the synthesis of Built-In Self-Test (BIST) logic. The proposed solution is based on an integer linear programming (ILP) formulation which builds on an existing Propositional Satisfiability (SAT) model for test pattern generation. The resulting ILP formulation is linear on the size of the original SAT model for test generation, which is linear on the size of the circuit. Nevertheless, the resulting ILP instances represent complex optimization problems, that require dedicated ILP algorithms. Preliminary results on benchmark circuits validate the practical applicability of the test pattern minimization model and associated ILP algorithm.