A method for generating weighted random test pattern
IBM Journal of Research and Development
A table of primitive binary polynomials
Mathematics of Computation
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Pattern generation for a deterministic BIST scheme
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Test vector encoding using partial LFSR reseeding
Proceedings of the IEEE International Test Conference 2001
On Calculating Efficient LFSR Seeds for Built-In Self Test
ETW '99 Proceedings of the 1999 IEEE European Test Workshop
Robust Search Algorithms for Test Pattern Generation
FTCS '97 Proceedings of the 27th International Symposium on Fault-Tolerant Computing (FTCS '97)
BIST RESEEDING WITH VERY FEW SEEDS
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
An Exact Solution to the Minimum Size Test Pattern Problem
ICCD '98 Proceedings of the International Conference on Computer Design
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
On the Size and Generation of Minimal N-Detection Tests
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
TACAS'08/ETAPS'08 Proceedings of the Theory and practice of software, 14th international conference on Tools and algorithms for the construction and analysis of systems
A Novel SMT-Based Technique for LFSR Reseeding
VLSID '12 Proceedings of the 2012 25th International Conference on VLSI Design
Multiple distributions for biased random test patterns
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test embedding with discrete logarithms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We propose a new method to derive a small number of LFSR seeds for Logic BIST to cover all detectable faults as a first-order satisfiability problem involving extended theories. We use an SMT (Satisfiability Modulo Theories) formulation to efficiently combine the tasks of test-generation and seed-computation. We make use of this formulation in an iterative seed-reduction flow which enables the "chaining" of hard-to-test faults using very few seeds. Experimental results demonstrate that up to 79% reduction in the number of seeds can be achieved.