A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters
Journal of Electronic Testing: Theory and Applications
Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST
Journal of Electronic Testing: Theory and Applications
On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST
Journal of Electronic Testing: Theory and Applications
A Ring Architecture Strategy for BIST Test Pattern Generation
Journal of Electronic Testing: Theory and Applications
Characteristic faults and spectral information for logic BIST
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Seed encoding with LFSRs and cellular automata
Proceedings of the 40th annual Design Automation Conference
A MIXED MODE BIST SCHEME BASED ON RESEEDING OF FOLDING COUNTERS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
TWO-DIMENSIONAL TEST DATA COMPRESSION FOR SCAN-BASED DETERMINISTIC BIST
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Scan-BIST based on transition probabilities
Proceedings of the 41st annual Design Automation Conference
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Testing Embedded Sequential Cores in Parallel Using Spectrum-Based BIST
IEEE Transactions on Computers
A seed selection procedure for LFSR-based random pattern generators
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Guided test generation for isolation and detection of embedded trojans in ics
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Column-matching based mixed-mode test pattern generator design technique for BIST
Microprocessors & Microsystems
Test Set Compression Through Alternation Between Deterministic and Pseudorandom Test Patterns
Journal of Electronic Testing: Theory and Applications
LFSR seed computation and reduction using SMT-based fault-chaining
Proceedings of the Conference on Design, Automation and Test in Europe
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Linear Feedback Shift Registers (LFSRs) are commonly used as pseudo-random test pattern generators (TPGs) in BIST schemes. This paper presents a fast simulation-based method to compute an efficient seed (initial state) of a given primitive polynomial LFSR TPG. The size of the LFSR, the primitive feedback polynomial and the length of the generated test sequence are a priori known. The method uses a deterministic test cube compression technique and produces a one-seed LFSR test sequence of a predefined test length that achieves high fault coverage. This technique can be applied either in pseudo-random testing for BISTed circuits containing few random resistant faults, or in pseudo-deterministic BIST where it allows the hardware generator overhead area to be reduced. Compared with existing methods, the proposed technique is able to deal with combinational circuits of great size and with a lot of primary inputs. Experimental results demonstrate the effectiveness of our method.