Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Test Data Decompression for Multiple Scan Designs with Boundary Scan
IEEE Transactions on Computers
Test vector encoding using partial LFSR reseeding
Proceedings of the IEEE International Test Conference 2001
On Calculating Efficient LFSR Seeds for Built-In Self Test
ETW '99 Proceedings of the 1999 IEEE European Test Workshop
Test point insertion based on path tracing
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
BIST RESEEDING WITH VERY FEW SEEDS
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
BUILT-IN RESEEDING FOR SERIAL BIST
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Test embedding with discrete logarithms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Column Parity Row Selection (CPRS) BIST Diagnosis Technique: Modeling and Analysis
IEEE Transactions on Computers
Deviation-based LFSR reseeding for test-data compression
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Scan-chain partition for high test-data compressibility and low shift power under routing constraint
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fully X-tolerant, very high scan compression
Proceedings of the 47th Design Automation Conference
Test Set Compression Through Alternation Between Deterministic and Pseudorandom Test Patterns
Journal of Electronic Testing: Theory and Applications
A new scheme of test data compression based on equal-run-length coding (ERLC)
Integration, the VLSI Journal
Achieving low capture and shift power in linear decompressor-based test compression environment
Microelectronics Journal
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Reseeding is used to improve fault coverage of pseudo-random testing. The seed corresponds to the initial state of the PRPG before filling the scan chain. In this paper, we present a technique for encoding a given seed by the number of clock cycles that the PRPG needs to run to reach it. This encoding requires many fewer bits than the bits of the seed itself. The cost is the time to reach the intended seed. We reduce this cost using the degrees of freedom (due to don't cares in test patterns) in solving the equations for the seeds. We show results for implementing our technique completely in on-chip hardware and for applying it from a tester. Simulations show that with low hardware overhead, the technique provides 100% single-stuck fault coverage. Also, when compared with conventional reseeding from an external tester or on-chip ROM, the technique reduces seed storage by up to 85%. We show how to apply the technique for both LFSRs and CA.