BUILT-IN RESEEDING FOR SERIAL BIST

Authors:
Ahmad A. Al-Yamani;Edward J. McCluskey
Affiliations:
-;-
Venue:
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Year:
2003

Citing 0
Cited 9

Seed encoding with LFSRs and cellular automata

Proceedings of the 40th annual Design Automation Conference
BIST-Guided ATPG

ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
EFSM Manipulation to Increase High-Level ATPG Effectiveness

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Test data compression scheme based on variable-to-fixed-plus-variable-length coding

Journal of Systems Architecture: the EUROMICRO Journal
Improving linear test data compression

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Integrated LFSR reseeding, test-access optimization, and test scheduling for core-based system-on-chip

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test Set Compression Through Alternation Between Deterministic and Pseudorandom Test Patterns

Journal of Electronic Testing: Theory and Applications
Test data compression using selective encoding of scan slices

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A new scheme of test data compression based on equal-run-length coding (ERLC)

Integration, the VLSI Journal

Quantified Score

Hi-index	0.00

Visualization

Abstract

Reseeding is used to improve fault coverage in BIST pseudo-randomtesting. Most of the work done on reseeding is basedon storing the seeds in an external tester. Besides its high cost,testing using automatic test equipment (ATE) makes it hard totest the circuit while in the system. In this paper, we present atechnique for built-in reseeding. Our technique requires nostorage for the seeds. The seeds are encoded in hardware. Theseeds we use are deterministic so 100% fault coverage can beachieved. Our technique causes no performance overhead anddoes not change the original circuit under test. Also, thetechnique we present is applicable for transition faults as wellas single-stuck-at faults. Built-in reseeding is based onexpanding every seed to as many ATPG patterns as possible.This is different from many existing reseeding techniques thatexpand every seed into a single ATPG pattern. This paperpresents the built-in reseeding algorithm together with ahardware synthesis algorithm and implementation.