IEEE Transactions on Computers - Special issue on fault-tolerant computing
Technology and design challenges for low power and high performance
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Test volume and application time reduction through scan chain concealment
Proceedings of the 38th annual Design Automation Conference
Scan Vector Compression/Decompression Using Statistical Coding
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
BIST-Aided Scan Test - A New Method for Test Cost Reduction
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
A Reconfigurable Shared Scan-in Architecture
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Application of Saluja-Karpovsky Compactors to Test Responses with Many Unknowns
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
BUILT-IN RESEEDING FOR SERIAL BIST
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Reducing Test Dat Volume Using LFSR Reseeding with Seed Compression
ITC '02 Proceedings of the 2002 IEEE International Test Conference
A SmartBIST Variant with Guaranteed Encoding
ATS '01 Proceedings of the 10th Asian Test Symposium
Reducing Test Application Time Through Test Data Mutation Encoding
Proceedings of the conference on Design, automation and test in Europe
Logic BIST for Large Industrial Designs: Real Issues and Case Studies
ITC '99 Proceedings of the 1999 IEEE International Test Conference
On test data volume reduction for multiple scan chain designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
XMAX: X-Tolerant Architecture for MAXimal Test Compression
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Test Compression and Hardware Decompression for Scan-Based SoCs
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Adjustable Width Linear Combinational Scan Vector Decompression
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
RL-huffman encoding for test compression and power reduction in scan applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
DATA COMPRESSION FOR MULTIPLE SCAN CHAINS USING DICTIONARIES WITH CORRECTIONS
ITC '04 Proceedings of the International Test Conference on International Test Conference
Variable-length input Huffman coding for system-on-a-chip test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
XID: Don't care identification of test patterns for combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
X-compact: an efficient response compaction technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test Data Compression Using Selective Sparse Storage
Journal of Electronic Testing: Theory and Applications
Test data compression using interval broadcast scan for embedded cores
Microelectronics Journal
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Virtual scan chains reordering using a RAM-based module for high test compression
Microelectronics Journal
| Hi-index | 0.00 |
We present a selective encoding method that reduces test data volume and test application time for scan testing of Intellectual Property (IP) cores. This method encodes the slices of test data that are fed to the scan chains in every clock cycle. To drive N scan chains, we use only c tester channels, where c = ⌈log2 (N + 1)⌉ + 2. In the best case, we can achieve compression by a factor of N/c using only one tester clock cycle per slice. We derive a sufficient condition on the distribution of care bits that allows us to achieve the best-case compression. We also derive a probabilistic lower bound on the compression for a given care-bit density. Unlike popular compression methods such as Embedded Deterministic Test (EDT), the proposed approach is suitable for IP cores because it does not require structural information for fault simulation, dynamic compaction, or interleaved test generation. The on-chip decoder is small, independent of the circuit under test and the test set, and it can be shared between different circuits. We present compression results for a number of industrial circuits and compare our results to other recent compression methods targeted at IP cores.