FCSCAN: an efficient multiscan-based test compression technique for test cost reduction
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Efficient test-data compression for IP cores using multilevel Huffman coding
Proceedings of the conference on Design, automation and test in Europe: Proceedings
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
State skip LFSRs: bridging the gap between test data compression and test set embedding for IP cores
Proceedings of the conference on Design, automation and test in Europe
Multilevel-Huffman test-data compression for IP cores with multiple scan chains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A diagnosis algorithm for extreme space compaction
Proceedings of the Conference on Design, Automation and Test in Europe
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Test data compression using selective encoding of scan slices
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We present two-dimensional (space/time) compression techniques that reduce test data volume and test application time for scan testing of intellectual property (IP) cores. We start with a set of test cubes and use the well-known concept of scan chain compatibility to determine a small number c of tester channels that are needed to drive m scan chains (c 驴 m). Next, we exploit logic dependencies between the test data for the scan chains to design a single-level decompression circuit based on two-input gates. We refer to these procedures collectively as width (space) compression. We then determine a small set of test patterns that can provide complete fault coverage when they are applied to the circuit under test using the c tester channels; this procedure is referred to as height (time) compression. In this way, structural information about the IP cores is not necessary for fault simulation, dynamic compaction, or test generation. The hardware overhead of the proposed approach is limited to the fan-out structure and a very small number of gates between the tester-driven external scan pins and the internal scan chains. Results are presented for the ISCAS-89 benchmarks and for four industrial circuits.