Multilevel-Huffman test-data compression for IP cores with multiple scan chains

Authors:
Xrysovalantis Kavousianos;Emmanouil Kalligeros;Dimitris Nikolos
Affiliations:
Computer Science Department, University of Ioannina, Ioannina, Greece;Information and Communication Systems Engineering Department, University of the Aegean, Samos, Greece;Computer Engineering and Informatics Department, University of Patras, Patras, Greece
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2008

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Abstract

Various compression methods have been proposed for tackling the problem of increasing test-data volume of contemporary, core-based systems. Despite their effectiveness, most of the approaches that are based on classical codes (e.g., run-lengths, Huffman) cannot exploit the test-application-time advantage of multiple-scan-chain cores, since they are not able to perform parallel decompression of the encoded data. In this paper, we take advantage of the inherent parallelism of Huffman decoding and we present a generalized multilevel Huffman-based compression approach that is suitable for cores with multiple scan chains. The size of the encoded data blocks is independent of the slice size (i.e., the number of scan chains), and thus it can be adjusted so as to maximize the compression ratio. At the same time, the parallel data-block decoding ensures the exploitation of most of the scan chains' parallelism. The proposed decompression architecture can be easily modified to suit any Huffman-based compression scheme.