Multilevel-Huffman test-data compression for IP cores with multiple scan chains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Scan test for SoC has now suffered large data volume and test application time. In this paper, we propose and demonstrate an Adaptive Encoding scheme to reduce the test volume and test time for SoC scan test. The scheme, instead of handling test data themselves, encodes them in "packets" according to difference bits of two consecutive test patterns. A decoder machine is designed to decode the compressed data and a repeat filling mechanism from the ATE is adopted to eliminate the synchronization problem. It supports variable block size and is flexible in encoding multi-core test patterns; therefore, the proposed method is effective in SoC scan test. Experimental results show that on average the scheme achieves 73% reduction in test data and more than 16 times of speedup in test application time.