Proceedings of the conference on Design, automation and test in Europe - Volume 2
3-Stage Variable Length Continuous-Flow Scan Vector Decompression Scheme
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Combining dictionary coding and LFSR reseeding for test data compression
Proceedings of the 41st annual Design Automation Conference
Adjustable Width Linear Combinational Scan Vector Decompression
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
XPAND: An Efficient Test Stimulus Compression Technique
IEEE Transactions on Computers
Survey of Test Vector Compression Techniques
IEEE Design & Test
SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test scheduling
Proceedings of the conference on Design, automation and test in Europe
State skip LFSRs: bridging the gap between test data compression and test set embedding for IP cores
Proceedings of the conference on Design, automation and test in Europe
Multilevel-Huffman test-data compression for IP cores with multiple scan chains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Improving linear test data compression
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Deviation-based LFSR reseeding for test-data compression
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
LFSR-based test-data compression with self-stoppable seeds
Proceedings of the Conference on Design, Automation and Test in Europe
Test Set Compression Through Alternation Between Deterministic and Pseudorandom Test Patterns
Journal of Electronic Testing: Theory and Applications
Time-multiplexed compressed test of SOC designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Correlation-based rectangular encoding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Nine-coded compression technique for testing embedded cores in socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Capture-power-aware test data compression using selective encoding
Integration, the VLSI Journal
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Localized delay defects, like resistive shorts, resistiveopens, etc., can be effectively detected by testing the longesttestable path through each wire (or gate) in the circuit. Sucha delay test set is referred to as a longest-path-per-wire testset. ...