Using a single input to support multiple scan chains
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Reduction of SOC test data volume, scan power and testing time using alternating run-length codes
Proceedings of the 39th annual Design Automation Conference
Test vector decompression via cyclical scan chains and its application to testing core-based designs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Test vector encoding using partial LFSR reseeding
Proceedings of the IEEE International Test Conference 2001
Efficient compression and application of deterministic patterns in a logic BIST architecture
Proceedings of the 40th annual Design Automation Conference
Reducing Test Application Time for Full Scan Embedded Cores
FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
Efficient Seed Utilization for Reseeding based Compression
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A SmartBIST Variant with Guaranteed Encoding
ATS '01 Proceedings of the 10th Asian Test Symposium
Reducing Test Application Time Through Test Data Mutation Encoding
Proceedings of the conference on Design, automation and test in Europe
On Test Data Volume Reduction for Multiple Scan Chain Designs
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
IEEE Transactions on Computers
Test data compression using dictionaries with selective entries and fixed-length indices
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on Computers
Adjustable Width Linear Combinational Scan Vector Decompression
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
XPAND: An Efficient Test Stimulus Compression Technique
IEEE Transactions on Computers
Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques
ITC '04 Proceedings of the International Test Conference on International Test Conference
DATA COMPRESSION FOR MULTIPLE SCAN CHAINS USING DICTIONARIES WITH CORRECTIONS
ITC '04 Proceedings of the International Test Conference on International Test Conference
Survey of Test Vector Compression Techniques
IEEE Design & Test
Power-Aware Test Data Compression for Embedded IP Cores
ATS '06 Proceedings of the 15th Asian Test Symposium
A Scan Chain Adjustment Technology for Test Power Reduction
ATS '06 Proceedings of the 15th Asian Test Symposium
Low Shift and Capture Power Scan Tests
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
System-on-a-chip test-data compression and decompression architectures based on Golomb codes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Variable-length input Huffman coding for system-on-a-chip test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient test vector compression scheme using selective Huffman coding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Ring generators - new devices for embedded test applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Ever-increasing test data volume and excessive test power are two of the main concerns of VLSI testing. The ''don't-care'' bits (also known as X-bits) in given test cube can be exploited for test data compression and/or test power reduction, and these techniques may contradict to each other because the very same X-bits are likely to be used for different optimization objectives. This paper proposes a capture-power-aware test compression scheme that is able to keep capture-power under a safe limit with low test compression ratio loss. Experimental results on benchmark circuits validate the effectiveness of the proposed solution.