Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
Test vector encoding using partial LFSR reseeding
Proceedings of the IEEE International Test Conference 2001
Test Data Compression for System-on-a-Chip Using Golomb Codes
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test data compression using dictionaries with selective entries and fixed-length indices
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Survey of Test Vector Compression Techniques
IEEE Design & Test
Proceedings of the conference on Design, automation and test in Europe
Nine-coded compression technique for testing embedded cores in socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Variable-length input Huffman coding for system-on-a-chip test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient test vector compression scheme using selective Huffman coding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Relationship Between Entropy and Test Data Compression
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
State-Sensitive X-Filling Scheme for Scan Capture Power Reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Compression-aware capture power reduction for at-speed testing
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Capture-power-aware test data compression using selective encoding
Integration, the VLSI Journal
Achieving low capture and shift power in linear decompressor-based test compression environment
Microelectronics Journal
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Growing test data volume and overtesting caused by excessive scan capture power are two of the major concerns for the industry when testing large integrated circuits. Various test data compression (TDC) schemes and low-power X-filling techniques were proposed to address the above problems. These methods, however, exploit the very same "don't-care" bits in the test cubes to achieve different objectives and hence may contradit to each other. In this work, we propose a generic framework for reducing scan capture power in test compression environment. Using the entropy of the test set to measure the impact of capture power-aware X-filling on the potential test compression ratio, the proposed holistic solution is able to keep capture power under a safe limit with little compression ratio loss for any fixed-length symbol-based TDC method. Experimental results on benchmark circuits demonstrate the efficacy of the proposed approach.