Compression-aware capture power reduction for at-speed testing

Authors:
Jia Li;Qiang Xu;Dong Xiang
Affiliations:
Tsinghua University, Beijing, CHINA;The Chinese University of Hong Kong, Shatin, Hong Kong;Tsinghua University, Beijing, CHINA
Venue:
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Year:
2011

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Abstract

Test compression has become a de facto technique in VLSI testing. Meanwhile, excessive capture power of at-speed testing has also become a serious concern. Therefore, it is important to co-optimize test power and compression ratio in at-speed testing. In this paper, a novel X-filling framework is proposed to reduce capture power of both LoC and LoS at-speed testing, which is applicable for different test compression schemes. The proposed technology has been validated by the experimental results on larger ITC'99 benchmark circuits.