Test set compaction algorithms for combinational circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Reduction of SOC test data volume, scan power and testing time using alternating run-length codes
Proceedings of the 39th annual Design Automation Conference
Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
Test vector encoding using partial LFSR reseeding
Proceedings of the IEEE International Test Conference 2001
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques
ITC '04 Proceedings of the International Test Conference on International Test Conference
Survey of Test Vector Compression Techniques
IEEE Design & Test
On reducing both shift and capture power for scan-based testing
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe
Variable-length input Huffman coding for system-on-a-chip test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
State-Sensitive X-Filling Scheme for Scan Capture Power Reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Scan power reduction in linear test data compression scheme
Proceedings of the 2009 International Conference on Computer-Aided Design
QC-fill: quick-and-cool X-filling for multicasting-based scan test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Journal of Electronic Testing: Theory and Applications
Low-power test in compression-based reconfigurable scan architectures
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
X-filling for simultaneous shift- and capture-power reduction in at-speed scan-based testing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test data compression using alternating variable run-length code
Integration, the VLSI Journal
Compression-aware capture power reduction for at-speed testing
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Pseudo-functional testing for small delay defects considering power supply noise effects
Proceedings of the International Conference on Computer-Aided Design
Scan power reduction for linear test compression schemes through seed selection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Large test data volume and high test power are two of the major concerns for the industry when testing large integrated circuits. With given test cubes in scan-based testing, the "don't-care" bits can be exploited for test data compression and/or test power reduction. Prior work either targets only one of these two issues or considers to reduce test data volume and scan shift power together. In this paper, we propose a novel capture power-aware test compression scheme that is able to keep scan capture power under a safe limit with little loss in test compression ratio. Experimental results on benchmark circuits demonstrate the efficacy of the proposed approach.