A Reconfigurable Shared Scan-in Architecture
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
CircularScan: A Scan Architecture for Test Cost Reduction
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Changing the Scan Enable during Shift
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Test Cost Reduction Through A Reconfigurable Scan Architecture
ITC '04 Proceedings of the International Test Conference on International Test Conference
A New ATPG Method for Efficient Capture Power Reduction During Scan Testing
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
New test data decompressor for low power applications
Proceedings of the 44th annual Design Automation Conference
Bounded Adjacent Fill for Low Capture Power Scan Testing
VTS '08 Proceedings of the 26th IEEE VLSI Test Symposium
Low power Illinois scan architecture for simultaneous power and test data volume reduction
Proceedings of the conference on Design, automation and test in Europe
On capture power-aware test data compression for scan-based testing
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Low-power scan operation in test compression environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
QC-fill: quick-and-cool X-filling for multicasting-based scan test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Scan Architecture With Align-Encode
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Scan-based testing of integrated circuits produces significant switching activity during shift and capture operations, dissipating excessive power levels and, possibly, resulting in an unexpected behavior of the design. The problem is further accentuated in compression-based scan; as don't care bits are exploited to compress test patterns, additional care bits are specified in the deliverable pattern, limiting the effectiveness of x-filling techniques. In this work, we propose a low-power test method for compression-based reconfigurable scan architectures. In addition to their key objective of minimizing Test Data Volume (TDV), we illustrate how the distribution of care bits in scan chains can be manipulated, using the different encoding configurations supported by the reconfigurable scan architecture, with the objective of reducing the number of transitions during test. Hence, peak and average power of shift and capture operations are effectively reduced. Experimental results, performed using one possible reconfigurable scan architecture as a case study, indicate that up to 50% power reduction is possible at the expense of an increase in TDV, while similar reduction levels are overhead-free in other reconfigurable scan architectures.