A New ATPG Method for Efficient Capture Power Reduction During Scan Testing

Authors:
Xiaoqing Wen;Seiji Kajihara;Kohei Miyase;Tatsuya Suzuki;Kewal K. Saluja;Laung-Terng Wang;Khader S. Abdel-Hafez;Kozo Kinoshita
Affiliations:
Kyushu Institute of Technology, Japan;Kyushu Institute of Technology, Japan;Japan Science and Technology Agency, Japan;Kyushu Institute of Technology, Japan;University of Wisconsin - Madison;SynTest Technologies;SynTest Technologies;Osaka Gakuin University, Japan
Venue:
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Year:
2006

Citing 0
Cited 16

Interactive presentation: On power-profiling and pattern generation for power-safe scan tests

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Variation-Tolerant, Power-Safe Pattern Generation

IEEE Design & Test
Methodology for low power test pattern generation using activity threshold control logic

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Scan Division Algorithm for Shift and Capture Power Reduction for At-Speed Test Using Skewed-Load Test Application Strategy

Journal of Electronic Testing: Theory and Applications
Scan-in and Scan-out Transition Co-optimization Through Modelling Generalized Serial Transformations

Journal of Electronic Testing: Theory and Applications
Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing

Journal of Electronic Testing: Theory and Applications
Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification

Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A power-effective scan architecture using scan flip-flops clustering and post-generation filling

Proceedings of the 19th ACM Great Lakes symposium on VLSI
System-on-Chip Test Architectures: Nanometer Design for Testability

System-on-Chip Test Architectures: Nanometer Design for Testability
Low-power scan testing for test data compression using a routing-driven scan architecture

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
LPTest: a Flexible Low-Power Test Pattern Generator

Journal of Electronic Testing: Theory and Applications
Power supply noise reduction for at-speed scan testing in linear-decompression environment

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On the Application of Dynamic Scan Chain Partitioning for Reducing Peak Shift Power

Journal of Electronic Testing: Theory and Applications
On reducing scan shift activity at RTL

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-power test in compression-based reconfigurable scan architectures

SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
Defect aware X-filling for low-power scan testing

Proceedings of the Conference on Design, Automation and Test in Europe

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Abstract

Path delay fault simulation performance on multi-cycle delay paths common in industrial designs is discussed using paths from a large block in a microprocessor and a functional test vector suite. We profile fault simulation performance using a novel ...