ATPG for Heat Dissipation Minimization During Test Application
IEEE Transactions on Computers
Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits
IEEE Transactions on Computers
An analysis of power reduction techniques in scan testing
Proceedings of the IEEE International Test Conference 2001
A novel scan architecture for power-efficient, rapid test
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Reducing Power Dissipation during Test Using Scan Chain Disable
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Controlling Peak Power During Scan Testing
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Design of Routing-Constrained Low Power Scan Chains
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques
ITC '04 Proceedings of the International Test Conference on International Test Conference
A New ATPG Method for Efficient Capture Power Reduction During Scan Testing
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Low Shift and Capture Power Scan Tests
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scan chain clustering for test power reduction
Proceedings of the 45th annual Design Automation Conference
Low-power scan testing and test data compression for system-on-a-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test pattern generation and clock disabling for simultaneous test time and power reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, we propose a novel way to save test power, using the DFT based technique as basic method and post-generation filling as complementary. In this architecture, two methods of clustering flip-flops into scan chains are presented. One is clustering scan flip-flops into two parts to save capture power, and the other is clustering scan flip-flops of each part into scan chains to save shift power. By partitioning the scan flip-flops into two parts, the capture operation is cut into two sequential steps, which can effectively reduce the capture power. By partitioning flip-flops with common successors into one chain, we can make sure that, only one or a small part of scan chains are active during the shifting phase. For other scan chains, filling strategy is used as complementary method to further reduce test power. This architecture can effectively reduce the test time too. Experimental results show that average power reduction of 91.81% and average peak power reduction of 49.35% can be achieved, comparing to the ordinary full-scan architecture.