A critical-path-aware partial gating approach for test power reduction
ACM Transactions on Design Automation of Electronic Systems (TODAES)
New test data decompressor for low power applications
Proceedings of the 44th annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On reducing both shift and capture power for scan-based testing
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Scan-in and Scan-out Transition Co-optimization Through Modelling Generalized Serial Transformations
Journal of Electronic Testing: Theory and Applications
Proceedings of the conference on Design, automation and test in Europe
Opposite-phase register switching for peak current minimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A Novel ATPG Method for Capture Power Reduction during Scan Testing
IEICE - Transactions on Information and Systems
A power-effective scan architecture using scan flip-flops clustering and post-generation filling
Proceedings of the 19th ACM Great Lakes symposium on VLSI
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
LPTest: a Flexible Low-Power Test Pattern Generator
Journal of Electronic Testing: Theory and Applications
Low-power scan operation in test compression environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
QC-fill: quick-and-cool X-filling for multicasting-based scan test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Graph theoretic approach for scan cell reordering to minimize peak shift power
Proceedings of the 20th symposium on Great lakes symposium on VLSI
On the Application of Dynamic Scan Chain Partitioning for Reducing Peak Shift Power
Journal of Electronic Testing: Theory and Applications
Scan-Cell Reordering for Minimizing Scan-Shift Power Based on Nonspecified Test Cubes
ACM Transactions on Design Automation of Electronic Systems (TODAES)
QC-fill: an X-fill method for quick-and-cool scan test
Proceedings of the Conference on Design, Automation and Test in Europe
X-filling for simultaneous shift- and capture-power reduction in at-speed scan-based testing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Correlation-based rectangular encoding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Observation-Oriented ATPG and Scan Chain Disabling for Capture Power Reduction
Journal of Electronic Testing: Theory and Applications
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This paper presents a procedure for modifying a given set of scan vectors so that the peak power uring scan testing is kept below a specified limit without reducing fault coverage. The propose approach works for any conventional full-scan design -no extra design-for-test (DFT) logic is required. If the peak power in a clock cycle during scan testing exceeds a specified limit (which depends on the amount of peak power that can be safely handle without causing a failure that woul not occur during normal functional operation) then a "peak power violation occurs. Given a set of scan vectors, simulation is done to identify and classify the scan vectors that are causing peak power violations during scan testing. The problem scan vectors are then modified in a way that eliminates the peak power violations while preserving the fault coverage. Experimental results indicate the proposed procedure is very effective in controlling peak power.