On reducing both shift and capture power for scan-based testing

Authors:
Jia Li;Qiang Xu;Yu Hu;Xiaowei Li
Affiliations:
ICT, Chinese Academy of Sciences, Beijing and Graduate University of Chinese Academy of Sciences, Beijing;The Chinese University of Hong Kong, Hong Kong and Institute of Advanced Integration Technology, CAS/CUHK, Shenzhen;ICT, Chinese Academy of Sciences, Beijing;ICT, Chinese Academy of Sciences, Beijing
Venue:
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Year:
2008

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Abstract

Power consumption in scan-based testing is a major concern nowadays. In this paper, we present a new X-filling technique to reduce both shift power and capture power during scan tests, namely LSC-filling. The basic idea is to use as few as possible X-bits to keep the capture power under the peak power limit of the circuit under test (CUT), while using the remaining X-bits to reduce the shift power to cut down the CUT's average power consumption during scan tests as much as possible. In addition, by carefully selecting the X-filling order, our X-filling technique is able to achieve lower capture power when compared to existing methods. Experimental results on ISCAS'89 benchmark circuits show the effectiveness of the proposed methodology.