Low Shift and Capture Power Scan Tests

Authors:
Santiago Remersaro;Xijiang Lin;Sudhakar M. Reddy;Irith Pomeranz;Janusz Rajski
Affiliations:
University of Iowa, Iowa City;Mentor Graphics Corporation, Wilsonville, OR;University of Iowa, Iowa City;Purdue University, West Lafayette, IN;Mentor Graphics Corporation, Wilsonville, OR
Venue:
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Year:
2007

Citing 0
Cited 12

Scan-Based Tests with Low Switching Activity

IEEE Design & Test
Methodology for low power test pattern generation using activity threshold control logic

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
On reducing both shift and capture power for scan-based testing

Proceedings of the 2008 Asia and South Pacific Design Automation Conference
iFill: an impact-oriented X-filling method for shift- and capture-power reduction in at-speed scan-based testing

Proceedings of the conference on Design, automation and test in Europe
Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification

Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A power-effective scan architecture using scan flip-flops clustering and post-generation filling

Proceedings of the 19th ACM Great Lakes symposium on VLSI
Bit-swapping LFSR and scan-chain ordering: a novel technique for peak- and average-power reduction in scan-based BIST

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
LPTest: a Flexible Low-Power Test Pattern Generator

Journal of Electronic Testing: Theory and Applications
X-filling for simultaneous shift- and capture-power reduction in at-speed scan-based testing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Switching activity as a test compaction heuristic for transition faults

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Capture-power-aware test data compression using selective encoding

Integration, the VLSI Journal
Power-safe application of tdf patterns to flip-chip designs during wafer test

ACM Transactions on Design Automation of Electronic Systems (TODAES)

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Abstract

Supply current and power dissipation during scan based test may be much higher than during normal circuit operation due to larger switching activity caused by the tests. Higher peak current demands may cause supply voltage droops causing good chips to fail at-speed tests. Higher average switching activity causes higher power dissipation and chip temperature that may cause hot spots and damage circuits under test. Several works have proposed methods to derive tests with lower peak and average switching activity during test response capture or during scan shifts. Some of these methods require additional hardware and modifications to the scan chains. In this paper we investigate a method to derive tests with reduced switching activity both during scan shifts and during test response captures. The method does not require additional hardware or modifications to the scan chains. The proposed method accepts a given test set and returns a test set of the same or smaller size with reduced switching activity. Experimental results on benchmark and industrial circuits are given.