ATPG for Heat Dissipation Minimization During Test Application
IEEE Transactions on Computers
Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
On Reducing Peak Current and Power during Test
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques
ITC '04 Proceedings of the International Test Conference on International Test Conference
Trends in manufacturing test methods and their implications
ITC '04 Proceedings of the International Test Conference on International Test Conference
A New ATPG Method for Efficient Capture Power Reduction During Scan Testing
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Low Shift and Capture Power Scan Tests
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Power supply noise reduction for at-speed scan testing in linear-decompression environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Improved weight assignment for logic switching activity during at-speed test pattern generation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
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This paper proposes a new technique of power-aware test pattern generation, wherein the test mode power constraints are specified using pseudo hardware logic functions (referred to as power constraint circuits) that augment the target circuit fed to the ATPG tool. The novelty of this approach is three-fold: (i) The ATPG tool only sees the enhanced circuit. This influences the generation of the test cubes themselves, as against post-processing of these cubes for a given pattern. (ii) Pattern generation can be driven to minimize test power according to a programmable switching activity threshold, and hence, is scalable. (iii) The same constraint circuit can also be effectively used for pattern filtering to isolate patterns which cause high switching activity. Additionally, the proposed method does not require any changes to the pattern generation tool or process. This paper describes the methodology, together with techniques for realizing the hardware circuit and specifying thresholds. Experimental results on various benchmark circuits (including an industrial design) are presented to show the effectiveness of this approach.