Methodology for low power test pattern generation using activity threshold control logic
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
On Composite Leakage Current Maximization
Journal of Electronic Testing: Theory and Applications
Globally optimized robust systems to overcome scaled CMOS reliability challenges
Proceedings of the conference on Design, automation and test in Europe
End-to-end register data-flow continuous self-test
Proceedings of the 36th annual international symposium on Computer architecture
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
ZerehCache: armoring cache architectures in high defect density technologies
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Utilizing On-chip Resources for Testing Embedded Mixed-signal Cores
Journal of Electronic Testing: Theory and Applications
A self-adaptive system architecture to address transistor aging
Proceedings of the Conference on Design, Automation and Test in Europe
Power-safe application of tdf patterns to flip-chip designs during wafer test
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Driven by market applications in the areas of computing, networking, storage, optical, wireless, portable, and consumer electronics, semiconductor chips today are as diverse as ever. Confluence of multiple applications and rapid integration has also driven the heterogeneity of chips. Test methods have evolved with the products. However, the basic goals in testing remain the same: quality of product, recurring and non-recurring costs and time to market. In this paper we try to catalog some commonly used test methods, identify their associated DFT requirements and trends in terms of tester requirements. Given the diversity of semiconductors chips today such as various PLDs, volatile and non-volatile memories, analog, mixed signal, FPGA, ASIC, SOC, MEMs and processors , it is impossible for a paper of this nature to be fully comprehensive. So we limit our focus on processor, ASIC and SOCs.