Technology and design challenges for low power and high performance
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Robust SAT-Based Search Algorithm for Leakage Power Reduction
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Maximum Leakage Power Estimation for CMOS Circuits
VOLTA '99 Proceedings of the IEEE Alessandro Volta Memorial Workshop on Low-Power Design
On estimating bounds of the quiescent current for I/sub DDQ/ testin
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Simultaneous Subthreshold and Gate-Oxide Tunneling Leakage Current Analysis in Nanometer CMOS Design
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Efficient techniques for gate leakage estimation
Proceedings of the 2003 international symposium on Low power electronics and design
Gate oxide leakage current analysis and reduction for VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Implicit pseudo boolean enumeration algorithms for input vector control
Proceedings of the 41st annual Design Automation Conference
Circuit-Based Preprocessing of ILP and Its Applications in Leakage Minimization and Power Estimation
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Accurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100nm Circuits
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Trends in manufacturing test methods and their implications
ITC '04 Proceedings of the International Test Conference on International Test Conference
Zchaff2004: an efficient SAT solver
SAT'04 Proceedings of the 7th international conference on Theory and Applications of Satisfiability Testing
Models and algorithms for bounds on leakage in CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Leakage power bounds in CMOS digital technologies
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Sub-threshold, gate and reverse biased junction band-to-band tunneling leakage currents depend on the logic inputs of a CMOS circuit. In this paper, we consider all leakage currents together and generate pattern with the objective of maximizing the overall leakage current to avoid any optimism in leakage current estimation. The computation involves Boolean reasoning on a pre-characterized set of interconnected gates. This problem is known to be computationally intractable. We propose a heuristic with reduced complexity by looking for a lower and an upper bound instead. The bounds tighten progressively with computation and converge asymptotically on a provably exact solution. By appropriately setting the objective function, the same algorithm may also be applied to find the pattern that minimizes the leakage power in the system idle state, which is considered to be ~50% of the total power consumed in the current technology generations.