Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Edge-valued binary decision diagrams for multi-level hierarchical verification
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Recent directions in netlist partitioning: a survey
Integration, the VLSI Journal
Algebraic decision diagrams and their applications
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
Runtime mechanisms for leakage current reduction in CMOS VLSI circuits1,2
Proceedings of the 2002 international symposium on Low power electronics and design
Partition-based decision heuristics for image computation using SAT and BDDs
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Robust SAT-Based Search Algorithm for Leakage Power Reduction
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Analysis and minimization techniques for total leakage considering gate oxide leakage
Proceedings of the 40th annual Design Automation Conference
Maximum Leakage Power Estimation for CMOS Circuits
VOLTA '99 Proceedings of the IEEE Alessandro Volta Memorial Workshop on Low-Power Design
Explicit and implicit algorithms for binate covering problems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Models and algorithms for bounds on leakage in CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Leakage power bounds in CMOS digital technologies
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A combined gate replacement and input vector control approach for leakage current reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On Composite Leakage Current Maximization
Journal of Electronic Testing: Theory and Applications
A Fast Probability-Based Algorithm for Leakage Current Reduction Considering Controller Cost
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
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In a CMOS combinational logic circuit, the subthreshold leakage current in the standby state depends on the state of the inputs. In this paper we present a new approach to identify the minimum leakage set of input vectors (MLS). Applying a vector in the MLS is known as Input Vector Control (IVC), and has proven to be very useful in reducing gate oxide leakage and sub-threshold leakage in standby mode of operation. The approach presented here is based on Implicit Enumeration of integer-valued decision diagrams. Since the search space for minimum leakage vector increases exponentially with the number of primary inputs, the enumeration is done with respect to the minimum balanced cut of the digraph representation of the circuit. To reduce the switching power dissipated when the inputs are driven to a given state (during entry into and exit from the standby state), we extend the MLS algorithm to compute a bounded leakage set (BLS). Given a bound of standby leakage, we present an algorithm for computing minimal switching cost partial input vectors such that the leakage of the circuit is always less than the upper bound.