ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Minimizing stand-by leakage power in static CMOS circuits
Proceedings of the conference on Design, automation and test in Europe
Full-chip sub-threshold leakage power prediction model for sub-0.18 μm CMOS
Proceedings of the 2002 international symposium on Low power electronics and design
Runtime mechanisms for leakage current reduction in CMOS VLSI circuits1,2
Proceedings of the 2002 international symposium on Low power electronics and design
Algebric Decision Diagrams and Their Applications
Formal Methods in System Design
Robust SAT-Based Search Algorithm for Leakage Power Reduction
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
The complexity of theorem-proving procedures
STOC '71 Proceedings of the third annual ACM symposium on Theory of computing
Model-Based IDDQ Pass/Fail Limit Setting
IDDQ '98 Proceedings of the IEEE International Workshop on IDDQ Testing
Full chip leakage estimation considering power supply and temperature variations
Proceedings of the 2003 international symposium on Low power electronics and design
Statistical estimation of leakage current considering inter- and intra-die process variation
Proceedings of the 2003 international symposium on Low power electronics and design
An ASIC design methodology with predictably low leakage, using leakage-immune standard cells
Proceedings of the 2003 international symposium on Low power electronics and design
BerkMin: A Fast and Robust Sat-Solver
Proceedings of the conference on Design, automation and test in Europe
Implicit pseudo boolean enumeration algorithms for input vector control
Proceedings of the 41st annual Design Automation Conference
A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2004 international symposium on Low power electronics and design
An effective power mode transition technique in MTCMOS circuits
Proceedings of the 42nd annual Design Automation Conference
Enhanced leakage reduction Technique by gate replacement
Proceedings of the 42nd annual Design Automation Conference
Full-chip analysis of leakage power under process variations, including spatial correlations
Proceedings of the 42nd annual Design Automation Conference
Leakage minimization of nano-scale circuits in the presence of systematic and random variations
Proceedings of the 42nd annual Design Automation Conference
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Exact and heuristic approaches to input vector control for leakage power reduction
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Statistical delay computation considering spatial correlations
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Projection-based statistical analysis of full-chip leakage power with non-log-normal distributions
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
An algorithm to minimize leakage through simultaneous input vector control and circuit modification
Proceedings of the conference on Design, automation and test in Europe
Models and algorithms for bounds on leakage in CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical timing analysis under spatial correlations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Controlling NBTI degradation during static burn-in testing
Proceedings of the 16th Asia and South Pacific Design Automation Conference
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The control of leakage power consumption is a growing design challenge for current and future CMOS circuits. Among existing techniques, 'parking' a circuit in a minimum leakage state during its standby mode of operation requires minimal circuit modification and results in significant leakage reduction. In this paper we present a heuristic approach (referred to as MLVC) to determine the input vector which minimizes leakage for a combinational design. This approach utilizes approximate signal probabilities of internal nodes to aid in finding the minimum leakage vector. We utilize a probabilistic heuristic to select the next gate to be processed as well as to select the best state of the selected gate. A fast SAT solver is employed to ensure the consistency of the assignments that are made in this process. A variant of MLVC, referred to as MLVC-VAR, is also presented. MLVC-VAR includes the effect of random variations in leakage values due to process, voltage and temperature (PVT) variations. Including the effect of PVT variations for determining minimum leakage vector is crucial because leakage currents have an exponential dependence on power supply, threshold voltage and temperature. To the best of the authors' knowledge, no other minimum leakage vector determination work has to date included the effect of PVT variations. Experimental results indicate that our MLVC method has very low runtimes, with excellent accuracy compared to existing approaches. Further, the comparison of the mean and standard deviation of the circuit leakage values for MLVC with MLVC-VAR and an existing random vector generating approach proves the need for considering these variations while determining the minimum leakage vector. MLVC-VAR reports, on average, about 9.69% improvement over MLVC with similar runtimes and 5.98% improvement over the random vector generation approach with significantly lower runtimes.