Full-chip sub-threshold leakage power prediction model for sub-0.18 μm CMOS
Proceedings of the 2002 international symposium on Low power electronics and design
Proceedings of the 40th annual Design Automation Conference
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Statistical estimation of leakage current considering inter- and intra-die process variation
Proceedings of the 2003 international symposium on Low power electronics and design
Parametric yield estimation considering leakage variability
Proceedings of the 41st annual Design Automation Conference
Full-chip analysis of leakage power under process variations, including spatial correlations
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 42nd annual Design Automation Conference
Asymptotic probability extraction for non-normal distributions of circuit performance
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Projection-based performance modeling for inter/intra-die variations
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
PRIMA: passive reduced-order interconnect macromodeling algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical analysis of full-chip leakage power considering junction tunneling leakage
Proceedings of the 44th annual Design Automation Conference
Statistical performance modeling and optimization
Foundations and Trends in Electronic Design Automation
Full-chip leakage current estimation based on statistical sampling techniques
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Proceedings of the 45th annual Design Automation Conference
A probabilistic technique for full-chip leakage estimation
Proceedings of the 13th international symposium on Low power electronics and design
Proceedings of the 46th Annual Design Automation Conference
Statistical modeling and analysis of chip-level leakage power by spectral stochastic method
Integration, the VLSI Journal
Proceedings of the 2009 International Conference on Computer-Aided Design
Efficient additive statistical leakage estimation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A linear statistical analysis for full-chip leakage power with spatial correlation
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Proceedings of the 47th Design Automation Conference
Proceedings of the 47th Design Automation Conference
Full-chip leakage analysis for 65nm CMOS technology and beyond
Integration, the VLSI Journal
Digital design at a crossroads: how to make statistical design methodologies industrially relevant
Proceedings of the Conference on Design, Automation and Test in Europe
On confidence in characterization and application of variation models
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Chip level statistical leakage power estimation using generalized extreme value distribution
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
On the Impact of Manufacturing Process Variations on the Lifetime of Sensor Networks
ACM Transactions on Embedded Computing Systems (TECS)
Statistical full-chip total power estimation considering spatially correlated process variations
Integration, the VLSI Journal
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In this paper we propose a novel projection-based algorithm to estimate the full-chip leakage power with consideration of both inter-die and intra-die process variations. Unlike many traditional approaches that rely on log-Normal approximations, the proposed algorithm applies a novel projection method to extract a low-rank quadratic model of the logarithm of the full-chip leakage current and, therefore, is not limited to log-Normal distributions. By exploring the underlying sparse structure of the problem, an efficient algorithm is developed to extract the non-log-Normal leakage distribution with linear computational complexity in circuit size. In addition, an incremental analysis algorithm is proposed to quickly update the leakage distribution after changes to a circuit are made. Our numerical examples in a commercial 90nm CMOS process demonstrate that the proposed algorithm provides 4x error reduction compared with the previously proposed log-Normal approximations, while achieving orders of magnitude more efficiency than a Monte Carlo analysis with 104 samples.