A fast algorithm for particle simulations
Journal of Computational Physics
SIAM Journal on Scientific and Statistical Computing
Analysis and minimization techniques for total leakage considering gate oxide leakage
Proceedings of the 40th annual Design Automation Conference
The rapid evaluation of potential fields in particle systems
The rapid evaluation of potential fields in particle systems
Full-chip analysis of leakage power under process variations, including spatial correlations
Proceedings of the 42nd annual Design Automation Conference
Projection-based statistical analysis of full-chip leakage power with non-log-normal distributions
Proceedings of the 43rd annual Design Automation Conference
Modeling and estimation of full-chip leakage current considering within-die correlation
Proceedings of the 44th annual Design Automation Conference
Statistical analysis of full-chip leakage power considering junction tunneling leakage
Proceedings of the 44th annual Design Automation Conference
Proceedings of the 45th annual Design Automation Conference
Statistical modeling and analysis of chip-level leakage power by spectral stochastic method
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A precorrected-FFT method for electrostatic analysis of complicated 3-D structures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A linear statistical analysis for full-chip leakage power with spatial correlation
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Proceedings of the 47th Design Automation Conference
Proceedings of the 47th Design Automation Conference
Fast Statistical Full-Chip Leakage Analysis for Nanometer VLSI Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Statistical full-chip total power estimation considering spatially correlated process variations
Integration, the VLSI Journal
Leak-Gauge: A late-mode variability-aware leakage power estimation framework
Microprocessors & Microsystems
| Hi-index | 0.00 |
Statistical full-chip leakage analysis considering spatial correlation is highly expensive due to its O(N2) complexity for logic circuits with N gates. Although efforts have been made to reduce the cost at the loss of accuracy, existing methods are still unsuitable for large-scale problems. In this paper we resolve the problem by re-formulating the computation to one that can be done efficiently using a well-developed technique that has been widely used in fast EM simulation and machine learning areas. The resulting algorithm is provably of O(N) or O(N log N) complexity with well-defined and easily-controlled error bounds. Experiments show that using the proposed method it is feasible to handle milliongate circuits within only a few minutes on a regular desktop PC. The corresponding error is less than 0.5% compared to exhausted computation that takes more than 3 days. The proposed method is about 300X faster and 10X more accurate compared to existing grid-approximation method.