Efficient power estimation for highly correlated input streams
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
Full-chip sub-threshold leakage power prediction model for sub-0.18 μm CMOS
Proceedings of the 2002 international symposium on Low power electronics and design
A symbolic simulation approach in resolving signals' correlation
SS '96 Proceedings of the 29th Annual Simulation Symposium (SS '96)
Proceedings of the 2003 international symposium on Low power electronics and design
Statistical analysis of subthreshold leakage current for VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Accurate SER Estimation Method Based on Propagation Probability
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Full-chip analysis of leakage power under process variations, including spatial correlations
Proceedings of the 42nd annual Design Automation Conference
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Considering process variations during system-level power analysis
Proceedings of the 2006 international symposium on Low power electronics and design
Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Proceedings of the 2009 International Conference on Computer-Aided Design
Statistical leakage estimation based on sequential addition of cell leakage currents
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast Statistical Full-Chip Leakage Analysis for Nanometer VLSI Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Accurate Estimation of Leakage Power Variability in Sub-micrometer CMOS Circuits
DSD '12 Proceedings of the 2012 15th Euromicro Conference on Digital System Design
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Leakage power has already become the major contributor to the total on-chip power consumption, rendering its estimation a necessary step in the IC design flow. The problem is further exacerbated with the increasing uncertainty in the manufacturing process known as process variability. We develop a method to estimate the variation of leakage power in the presence of both intra-die and inter-die process variability. Various complicating issues of leakage prediction such as spatial correlation of process parameters, the effect of different input states of gates on the leakage, and DIBL and stack effects are taken into account while we model the simultaneous variability of the two most critical process parameters, threshold voltage and effective channel length. Our subthreshold leakage current model is shown to fit closely on the HSPICE Monte Carlo simulation data with an average coefficient of determination (R^2) value of 0.9984 for all the cells of a standard library. We demonstrate the adjustability of this model to wider ranges of variation and its extendability to future technology scalings. We also present a complete framework for estimation of full-chip leakage power and show that our framework which we call Leak-Gauge, imposes little timing penalty on the system design flow and is applicable to real design cases.