Accurate estimation and modeling of total chip leakage considering inter- & intra-die process variations

Authors:
A. Agarwal;Kunhyuk Kang;K. Roy
Affiliations:
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA;Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA;Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Venue:
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Year:
2005

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Abstract

In this paper we propose an accurate estimation and modeling of total circuit leakage distribution, considering both inter- and intra-die variations (variation in L, T/sub ox/ and random dopant fluctuation). Since, the total leakage in a circuit depends on leakage in a transistor, integration of transistors in a logic gate, and the gate topology in a circuit block, we model the total circuit leakage distribution at all levels of circuit design, while taking the different correlations among transistors, logic gates, circuit topology, and input vectors into account. The proposed model accurately estimates both statistical information (mean and variance) and the shape of the leakage distribution. We have verified the model using Monte Carlo simulation using devices of 50nm effective length and analyzed the results to enumerate the effect of different process parameters on individual components of total leakage.