Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
Full-chip sub-threshold leakage power prediction model for sub-0.18 μm CMOS
Proceedings of the 2002 international symposium on Low power electronics and design
Modeling and analysis of leakage power considering within-die process variations
Proceedings of the 2002 international symposium on Low power electronics and design
Design Challenges of Technology Scaling
IEEE Micro
Proceedings of the 40th annual Design Automation Conference
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Full chip leakage estimation considering power supply and temperature variations
Proceedings of the 2003 international symposium on Low power electronics and design
Proceedings of the 2003 international symposium on Low power electronics and design
Statistical analysis of subthreshold leakage current for VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Early Assessment of Leakage Power for System Level Design
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Probabilistic dual-Vth leakage optimization under variability
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Probabilistic evaluation of solutions in variability-driven optimization
Proceedings of the 2006 international symposium on Physical design
Statistically Aware SRAM Memory Array Design
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Monte Carlo-Alternative Probabilistic Simulations for Analog Systems
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
FPGA device and architecture evaluation considering process variations
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Robust estimation of parametric yield under limited descriptions of uncertainty
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Impact of process variations on multicore performance symmetry
Proceedings of the conference on Design, automation and test in Europe
Device-aware yield-centric dual-Vt design under parameter variations in nanoscale technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Impact of Process and Temperature Variations on Network-on-Chip Design Exploration
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Frequency and yield optimization using power gates in power-constrained designs
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Full-chip model for leakage-current estimation considering within-die correlation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Accurate estimation of vector dependent leakage power in the presence of process variations
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Power grid analysis and verification considering temperature variations
Microelectronics Journal
Leakage power characterization considering process variations
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Statistical Timing and Power Optimization of Architecture and Device for FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Power yield analysis under process and temperature variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Workload assignment considering NBTI degradation in multicore systems
ACM Journal on Emerging Technologies in Computing Systems (JETC) - Special Issue on Reliability and Device Degradation in Emerging Technologies and Special Issue on WoSAR 2011
| Hi-index | 0.00 |
This paper presents a probabilistic framework for full-chip estimation of subthreshold leakage power distribution considering both within-die and die-to-die variations in process (P), temperature (T) and supply voltage (V). The results obtained under this framework are compared to BSIM results and are found to be more accurate in comparison to those obtained from existing statistical models. Using this framework, a quantitative analysis of the relative sensitivities of subthreshold leakage to P-T-V variations has been presented. For the first time, the effects of die-to-die channel length and temperature variations on subthreshold leakage are studied in combination with all within-die variations. It has been shown that for accurate estimation of subthreshold leakage, it is important to consider die-to-die temperature variations which can significantly increase the leakage power due to electrothermal couplings between power and temperature. Furthermore, the full-chip leakage power distribution arising due to both within-die and die-to-die P-T-V is calculated, which is subsequently used to estimate the leakage constrained yield under the impact of these variations. The calculations show that the yield is significantly lowered under the impact of within-die and die-to-die process and temperature variations.