Early Assessment of Leakage Power for System Level Design

Authors:
C. Talarico;B. Pillilli;K. L. Vakati;J. M. Wang
Affiliations:
University of Arizona, Tucson, AZ;University of Arizona, Tucson, AZ;University of Arizona, Tucson, AZ;University of Arizona, Tucson, AZ
Venue:
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Year:
2005

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Abstract

This paper presents a system level methodology for analyzing leakage power in the early stages of a system design. The assessment of leakage takes into accounts the simultaneous effect of threshold-voltage (Vt), oxide thickness (tox), device width (W), the inputs applied and statistical process variations. The approach has been validated by applying it to the design of a digital signal processing system. The results indicate that our power estimation technique is within 10% of SPICE, with the benefit of executing 15X faster.