Power analysis of embedded software: a first step towards software power minimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Architectural power analysis: the dual bit type method
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy characterization based on clustering
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Power macromodeling for high level power estimation
DAC '97 Proceedings of the 34th annual Design Automation Conference
Profile-driven program synthesis for evaluation of system power dissipation
DAC '97 Proceedings of the 34th annual Design Automation Conference
A framework for estimation and minimizing energy dissipation of embedded HW/SW systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
Incorporating cores into system-level specification
Proceedings of the 11th international symposium on System synthesis
Cycle-accurate simulation of energy consumption in embedded systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Interface and cache power exploration for core-based embedded system design
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
A hybrid approach for core-based system-level power modeling
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
PowerPlay-Fast Dynamic Power Estimation Based on Logic Simulation
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Efficient Power Estimation Techniques for HW/SW Systems
VOLTA '99 Proceedings of the IEEE Alessandro Volta Memorial Workshop on Low-Power Design
Towards a high-level power estimation capability [digital ICs]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Information theoretic measures for power analysis [logic design]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-level power modeling, estimation, and optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast system-level power profiling for battery-efficient system design
Proceedings of the tenth international symposium on Hardware/software codesign
A Framework for Design Space Exploration of Parameterized VLSI Systems
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Interconnect-based system-level energy and power prediction to guide architecture exploration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Early Assessment of Leakage Power for System Level Design
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Integrating functional and power simulation in embedded systems design
Journal of Embedded Computing - Low-power Embedded Systems
Accurate and fast system-level power modeling: An XScale-based case study
ACM Transactions on Embedded Computing Systems (TECS) - Special Section LCTES'05
Accurate and fast system-level power modeling: An XScale-based case study
ACM Transactions on Embedded Computing Systems (TECS)
Multiprocessor performance estimation using hybrid simulation
Proceedings of the 45th annual Design Automation Conference
Variation-aware system-level power analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast architecture evaluation of heterogeneous MPSoCs by host-compiled simulation
Proceedings of the 15th International Workshop on Software and Compilers for Embedded Systems
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Our earlier work for fast evaluation of power consumption of general cores in a system-on-a-chip described techniques that involved isolating high-level instructions of a core, measuring gate-level power consumption per instruction, and then annotating a system-level simulation model with the obtained data. In this work, we describe a method for speeding up the evaluation further, through the use of instruction traces and trace simulators for every core, not just microprocessor cores. Our method shows noticeable speedups at an acceptable loss of accuracy. We show that reducing trace sizes can speed up the method even further. The speedups allow for more extensive system-level power exploration and hence better optimization.