Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Potential-driven statistical ordering of transformations
DAC '97 Proceedings of the 34th annual Design Automation Conference
Profile-driven program synthesis for evaluation of system power dissipation
DAC '97 Proceedings of the 34th annual Design Automation Conference
COSYN: hardware-software co-synthesis of embedded systems
DAC '97 Proceedings of the 34th annual Design Automation Conference
A framework for estimation and minimizing energy dissipation of embedded HW/SW systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
Interface exploration for reduced power in core-based systems
Proceedings of the 11th international symposium on System synthesis
Reuse methodology manual: for system-on-a-chip designs
Reuse methodology manual: for system-on-a-chip designs
Power estimation for architectural exploration of HW/SW communication on system-level buses
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Introducing Core-Based System Design
IEEE Design & Test
Logic and system design for low power consumption
Logic and system design for low power consumption
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Fast cache and bus power estimation for parameterized system-on-a-chip design
DATE '00 Proceedings of the conference on Design, automation and test in Europe
A hybrid approach for core-based system-level power modeling
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Trace-driven system-level power evaluation of system-on-a-chip peripheral cores
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Parameterised system design based on genetic algorithms
Proceedings of the ninth international symposium on Hardware/software codesign
Instruction-based system-level power evaluation of system-on-a-chip peripheral cores
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Data memory design and exploration for low-power embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Memory Design and Exploration for Low Power, Embedded Systems
Journal of VLSI Signal Processing Systems - Special issue on signal processing systems design and implementation
System-level exploration for pareto-optimal configurations in parameterized systems-on-a-chip
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Low power system scheduling and synthesis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Framework for Design Space Exploration of Parameterized VLSI Systems
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Static analysis of parameterized loop nests for energy efficient use of data caches
Compilers and operating systems for low power
Methods for evaluating and covering the design space during early design development
Integration, the VLSI Journal
Disk layout optimization for reducing energy consumption
Proceedings of the 19th annual international conference on Supercomputing
Analyzing data reuse for cache reconfiguration
ACM Transactions on Embedded Computing Systems (TECS)
Making a case for split data caches for embedded applications
MEDEA '05 Proceedings of the 2005 workshop on MEmory performance: DEaling with Applications , systems and architecture
Tiny split data-caches make big performance impact for embedded applications
Journal of Embedded Computing - Issues in embedded single-chip multicore architectures
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Minimizing power consumption is of paramount importance during the design of embedded (mobile computing) systems that come as systems-on-a-chip, since interdependencies of design characteristics like power, performance, and area for various system parts (cores) become increasingly influential. In this scenario, interfaces play a key role since they allow one to control/exploit these interdependencies with the aim to meet design constraints like power. In this paper, we present the first comprehensive approach to explore this impact. We consider a whole system comprising a CPU, caches, a main memory and interfaces between those cores and demonstrate the high impact that an adequate adaptation between core parameters and interface parameters in terms of power consumption has. We especially found that cache parameters and bus configurations of cache buses have a significant impact in this respect. In addition, we made the important observation that optimizing for performance no longer implies that power is optimized as well in deep submicron technologies. Instead, we found out that especially for newer technologies, the relative interface power contribution increases, leading to scenarios where we obtain a real power/performance tradeoff. In summary, our explorations unveiled not yet investigated interdependencies that represent the first step towards future efforts to optimize/adapt interfaces and caches in core-based systems for low power designs.