Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Interface exploration for reduced power in core-based systems
Proceedings of the 11th international symposium on System synthesis
Working-zone encoding for reducing the energy in microprocessor address buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The case for a configure-and-execute paradigm
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Interface and cache power exploration for core-based embedded system design
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
A hybrid approach for core-based system-level power modeling
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Conflicting Criteria in Embedded System Design
IEEE Design & Test
Power/Performance Advantages of Victim Buffer in High-Performance Processors
VOLTA '99 Proceedings of the IEEE Alessandro Volta Memorial Workshop on Low-Power Design
Performance and Area Analysis of Processor Configurations with Scaling of Technology
Performance and Area Analysis of Processor Configurations with Scaling of Technology
A Performance/Area Workbench for Cache Memory Design
A Performance/Area Workbench for Cache Memory Design
An overview of evolutionary algorithms in multiobjective optimization
Evolutionary Computation
A Framework for Design Space Exploration of Parameterized VLSI Systems
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Processor-memory coexploration using an architecture description language
ACM Transactions on Embedded Computing Systems (TECS)
Safe integration of parameterized IP
Integration, the VLSI Journal - Special issue: IP and design reuse
A genetic algorithm high-level optimizer for complex datapath and data-flow digital systems
Applied Soft Computing
Efficient design space exploration for application specific systems-on-a-chip
Journal of Systems Architecture: the EUROMICRO Journal
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A recent reduction in the time to market has led to the development of a new approach to IP-based design in which a highly parametric pre-designed system-on-a-chip is configured according to the application it will have to execute. The greatest problems in this area regard exploration of the range of possible system configurations in search of the optimal configuration for a given system. There are, in fact, a number of parameters involved (bus sizes, cache configurations, software algorithms, etc.), each of which has a great impact on design constraints such as area, power and performance. An exhaustive analysis of all possible configurations is thus computationally unfeasible. In this paper we propose using genetic algorithms to determine the optimal configuration for a highly parametric system. The approach is applied to the search for the optimal configuration (in terms of area, power and mean access time) of a memory hierarchy involved in a given application.