Parameterised system design based on genetic algorithms
Proceedings of the ninth international symposium on Hardware/software codesign
Application-adaptive intelligent cache memory system
ACM Transactions on Embedded Computing Systems (TECS)
Using a Victim Buffer in an Application-Specific Memory Hierarchy
Proceedings of the conference on Design, automation and test in Europe - Volume 1
MEDEA '04 Proceedings of the 2004 workshop on MEmory performance: DEaling with Applications , systems and architecture
Microprocessors & Microsystems
Embedded Systems Design
Hi-index | 0.00 |
In this paper, we propose several different data cache configurations and analyze their power as well as performance implications on the processor. Unlike most existing work in low power microprocessor design, we explore a high performance processor with the latest innovations for performance. Using a detailed, architectural-level simulator, we evaluate full system performance using several different power/performance sensitive cache configurations. We then use the information obtained from the simulator to calculate the energy consumption of the memory hierarchy of the system. We show that victim buffer offers improved cache energy consumption over other techniques (10% compared to 3.8%), while at the same time provides comparable performance gains (3.54% compared to 3.45%).