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IEEE Transactions on Computers
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ACM Transactions on Computer Systems (TOCS)
Measuring VAX 8800 performance with a histogram hardware monitor
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Evaluating Associativity in CPU Caches
IEEE Transactions on Computers
Cache performance of the integer SPEC benchmarks on a RISC
ACM SIGARCH Computer Architecture News
The effect of context switches on cache performance
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
The interaction of architecture and operating system design
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
An analysis of MIPS and SPARC instruction set utilization on the SPEC benchmarks
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Generation and analysis of very long address traces
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Cache evaluation and the impact of workload choice
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
ACM Computing Surveys (CSUR)
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ACM Transactions on Computer Systems (TOCS)
IEEE Micro
Program optimization for a pipelined machine a case study
SIGMETRICS '84 Proceedings of the 1984 ACM SIGMETRICS conference on Measurement and modeling of computer systems
Performance Prediction by Benchmark and Machine Analysis
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Aspects of Cache Memory and Instruction
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Wisconsin Architectural Research Tool Set
ACM SIGARCH Computer Architecture News
Characterization of alpha AXP performance using TP and SPEC workloads
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
Design considerations for the PowerPC 601 microprocessor
IBM Journal of Research and Development
Resource allocation in a high clock rate microprocessor
ASPLOS VI Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
Trap-driven simulation with Tapeworm II
ASPLOS VI Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
Contrasting characteristics and cache performance of technical and multi-user commercial workloads
ASPLOS VI Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
Active memory: a new abstraction for memory-system simulation
Proceedings of the 1995 ACM SIGMETRICS joint international conference on Measurement and modeling of computer systems
Energy optimization of multi-level processor cache architectures
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Cache performance of fast-allocating programs
FPCA '95 Proceedings of the seventh international conference on Functional programming languages and computer architecture
Instruction fetching: coping with code bloat
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
CAT—caching address tags: a technique for reducing area cost of on-chip caches
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
SPAID: software prefetching in pointer- and call-intensive environments
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Proceedings of the 28th annual international symposium on Microarchitecture
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Correlation and aliasing in dynamic branch predictors
ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
Don't use the page number, but a pointer to it
ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
Increasing cache port efficiency for dynamic superscalar microprocessors
ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
Analysis of benchmark characteristics and benchmark performance prediction
ACM Transactions on Computer Systems (TOCS)
A quantitative analysis of loop nest locality
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
Improving cache performance with balanced tag and data paths
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
Trap-driven memory simulation with Tapeworm II
ACM Transactions on Modeling and Computer Simulation (TOMACS)
Active memory: a new abstraction for memory system simulation
ACM Transactions on Modeling and Computer Simulation (TOMACS)
On the use of SPEC benchmarks in computer architecture research
ACM SIGARCH Computer Architecture News
Trace-driven memory simulation: a survey
ACM Computing Surveys (CSUR)
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Proceedings of the 24th annual international symposium on Computer architecture
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IEEE Transactions on Computers
Digital system simulation: methodologies and examples
DAC '98 Proceedings of the 35th annual Design Automation Conference
CPU Cache Prefetching: Timing Evaluation of Hardware Implementations
IEEE Transactions on Computers
Modeling and Evaluating Design Alternatives for an On-Line Instrumentation System: A Case Study
IEEE Transactions on Software Engineering
Power and performance tradeoffs using various caching strategies
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
A Comparative Analysis of Cache Designs for Vector Processing
IEEE Transactions on Computers
The pool of subsectors cache design
ICS '99 Proceedings of the 13th international conference on Supercomputing
Quantifying loop nest locality using SPEC'95 and the perfect benchmarks
ACM Transactions on Computer Systems (TOCS)
Synthesis of application-specific memories for power optimization in embedded systems
Proceedings of the 37th Annual Design Automation Conference
Performance analysis using the MIPS R10000 performance counters
Supercomputing '96 Proceedings of the 1996 ACM/IEEE conference on Supercomputing
Parameterised system design based on genetic algorithms
Proceedings of the ninth international symposium on Hardware/software codesign
Fundamental limitations on the use of prefetching and stream buffers for scientific applications
Proceedings of the 2001 ACM symposium on Applied computing
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ICS '01 Proceedings of the 15th international conference on Supercomputing
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IEEE Micro
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IEEE Transactions on Computers
Compile-Time Based Performance Prediction
LCPC '99 Proceedings of the 12th International Workshop on Languages and Compilers for Parallel Computing
PACS '00 Proceedings of the First International Workshop on Power-Aware Computer Systems-Revised Papers
Trace-Driven Memory Simulation: A Survey
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Proceedings of the 40th annual Design Automation Conference
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HPC-ASIA '97 Proceedings of the High-Performance Computing on the Information Superhighway, HPC-Asia '97
Evaluation of cache consistency algorithm performance
MASCOTS '96 Proceedings of the 4th International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems
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ACM Transactions on Programming Languages and Systems (TOPLAS)
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WSC '04 Proceedings of the 36th conference on Winter simulation
A One's Complement Cache Memory
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
Cache aware mapping of streaming applications on a multiprocessor system-on-chip
Proceedings of the conference on Design, automation and test in Europe
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ACM Transactions on Architecture and Code Optimization (TACO)
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The authors consider whether SPECmarks, the figures of merit obtained from running the SPEC benchmarks under certain specified conditions, accurately indicate the performance to be expected from real, live work loads. Miss ratios for the entire set of SPEC92 benchmarks are measured. It is found that instruction cache miss ratios in general, and data cache miss ratios for the integer benchmarks, are quite low. Data cache miss ratios for the floating-point benchmarks are more in line with published measurements for real work loads.