Cache performance of the integer SPEC benchmarks on a RISC

Authors:
Dionisios N. Pnevmatikatos;Mark D. Hill
Affiliations:
Computer Sciences Department, University of Wisconsin-Madison, 1210 W. Dayton Street, Madison, WI;Computer Sciences Department, University of Wisconsin-Madison, 1210 W. Dayton Street, Madison, WI
Venue:
ACM SIGARCH Computer Architecture News
Year:
1990

Citing 6
Cited 9

How not to lie with statistics: the correct way to summarize benchmark results

Communications of the ACM - The MIT Press scientific computation series
Line (block) size choice for CPU cache memories

IEEE Transactions on Computers
A Case for Direct-Mapped Caches

Computer
Evaluating Associativity in CPU Caches

IEEE Transactions on Computers
Cache Memories

ACM Computing Surveys (CSUR)
Aspects of Cache Memory and Instruction

Aspects of Cache Memory and Instruction

High-bandwidth data memory systems for superscalar processors

ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Performance from architecture: comparing a RISC and a CISC with similar hardware organization

ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
The effect of real data cache behavior on the performance of a microarchitecture that supports dynamic scheduling

MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
The effectiveness of caches for vector processors

ICS '94 Proceedings of the 8th international conference on Supercomputing
Cache Profiling and the SPEC Benchmarks: A Case Study

Computer
Cache Performance of the SPEC92 Benchmark Suite

IEEE Micro
Measuring Cache and TLB Performance and Their Effect on Benchmark Runtimes

IEEE Transactions on Computers
The Performance of Counter- and Correlation-Based Schemes for Branch Target Buffers

IEEE Transactions on Computers
Do Object-Oriented Languages Need Special Hardware Support?

ECOOP '95 Proceedings of the 9th European Conference on Object-Oriented Programming

Quantified Score

Hi-index	0.01

Visualization

Abstract

SPEC is a new set of benchmark programs designed to measure a computer system's performance. The performance measured by benchmarks is strongly affected by the existence and configuration of cache memory. In this paper we evaluate the cache miss ratio of the Integer SPEC benchmarks. We show that the cache miss ratio depends strongly on the program, and that large caches are not completely exercised by these benchmarks.