ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
A Case for Direct-Mapped Caches
Computer
Comparing software and hardware schemes for reducing the cost of branches
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Cache performance of the integer SPEC benchmarks on a RISC
ACM SIGARCH Computer Architecture News
Branch history table prediction of moving target branches due to subroutine returns
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
SPEC benchmarks and competitive results
ACM SIGMETRICS Performance Evaluation Review
Strategies for branch target buffers
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
Branch strategy taxonomy and performance models
Branch strategy taxonomy and performance models
Alternative implementations of two-level adaptive branch prediction
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Improving the accuracy of dynamic branch prediction using branch correlation
ASPLOS V Proceedings of the fifth international conference on Architectural support for programming languages and operating systems
Predicting conditional branch directions from previous runs of a program
ASPLOS V Proceedings of the fifth international conference on Architectural support for programming languages and operating systems
Branch Target Buffer Design and Optimization
IEEE Transactions on Computers
A study of branch prediction strategies
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
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Branch target buffers, or BTBs, can be used to improve CPU performance by maintaining target and history information of previously executed branches. We present trace-driven simulation results comparing counter-based and correlation-based prediction schemes for a variety of branch target buffer sizes. We report relative performance estimates to show both the relative merits of various techniques and their effects on performance for current microprocessors. Our results indicate that counter-based schemes outperform correlation-based schemes for small buffers, but that the opposite becomes true as buffer size increases. This is due to the importance of hit ratio over prediction success in branch target buffer design. The transition point between counter- and correlation-based schemes is dependent on the size of the working set of dynamic branches for a given collection of benchmark programs.Our results also show that for small BTBs, hit ratio and hence performance decrease as the number of correlation bits increase. This is due to non-random distribution of correlation vectors causing increased collisions for BTB locations. Only when a BTB becomes large enough to capture the working set of a program驴s branch and correlation vector references do the expected benefits of correlation-based schemes manifest themselves.