Communications of the ACM
Communications of the ACM
Exploring the design space for a shared-cache multiprocessor
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
Complexity/performance tradeoffs with non-blocking loads
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
The effects of predicated execution on branch prediction
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
DAC '94 Proceedings of the 31st annual Design Automation Conference
PLDI '95 Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation
An analytical model of high performance superscalar-based multiprocessors
PACT '95 Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques
The performance impact of incomplete bypassing in processor pipelines
Proceedings of the 28th annual international symposium on Microarchitecture
Increasing cache port efficiency for dynamic superscalar microprocessors
ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
Fast message assembly using compact address relations
Proceedings of the 1996 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Area and performance tradeoffs in floating-point divide and square-root implementations
ACM Computing Surveys (CSUR)
Designing high bandwidth on-chip caches
Proceedings of the 24th annual international symposium on Computer architecture
Selective cache ways: on-demand cache resource allocation
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
The Performance of Counter- and Correlation-Based Schemes for Branch Target Buffers
IEEE Transactions on Computers
Selective Victim Caching: A Method to Improve the Performance of Direct-Mapped Caches
IEEE Transactions on Computers
Tradeoffs in the Design of Single Chip Multiprocessors
PACT '94 Proceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques
Hades-towards the design of an asynchronous superscalar processor
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
HPCA '95 Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture
FLASH: Foresighted Latency-Aware Scheduling Heuristic for Processors with Customized Datapaths
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
Functional Tests for RISC-microprocessors
Automation and Remote Control
Reconfigurable split data caches: a novel scheme for embedded systems
Proceedings of the 2007 ACM symposium on Applied computing
Interactive presentation: Functional and timing validation of partially bypassed processor pipelines
Proceedings of the conference on Design, automation and test in Europe
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The Alpha AXP 64-b architecture, which forms the basis for a series of high-performance computer systems, is described. The implementation of this architecture in the 21064 microprocessor is discussed. This 1.4-cm*1.7-cm CMOS chip incorporates 1.68 million transistors using a 0.75- mu m, three-metal process. Performance measurement results for a variety of commonly used benchmarks under both OpenVMS AXP V1 and DEC OSF/1 V1.2 are presented.