Communicating sequential processes
Communicating sequential processes
Software pipelining: an effective scheduling technique for VLIW machines
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
Communications of the ACM
An efficient resource-constrained global scheduling technique for superscalar and VLIW processors
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
ALU design and processor branch architecture
Microprocessing and Microprogramming
A 100-MIPS GaAs Asynchronous Microprocessor
IEEE Design & Test
An explicitly declared delayed-branch mechanism for a superscalar architecture
Selected papers of the short notes session on Euromicro '94
Register Locking in an Asynchronous Microprocessor
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
VLSI '93 Proceedings of the IFIP TC10/WG 10.5 International Conference on Very Large Scale Integration
Distributed simulation of asynchronous hardware: the program driven synchronization protocol
Journal of Parallel and Distributed Computing
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This paper uses Hades, a generic processor architecture aimed at single and multiple-instruction-issue asynchronous implementations, to illustrate some of the difficulties encountered in asynchronous processor design. Particular emphasis is placed on a decoupled operand forwarding mechanism which allows the last result of each functional unit to be forwarded to following instructions, yet completely separates forwarding from the register writeback operation.