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ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
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ICS '97 Proceedings of the 11th international conference on Supercomputing
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ICS '97 Proceedings of the 11th international conference on Supercomputing
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MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
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ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
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The memory bandwidth demands of modern microprocessors require the use of a multi-ported cache to achieve peak performance. However, multi-ported caches are costly to implement. In this paper we propose techniques for improving the bandwidth of a single cache port by using additional buffering in the processor, and by taking maximum advantage of a wider cache port. We evaluate these techniques using realistic applications that include the operating system. Our techniques using a single-ported cache achieve 91% of the performance of a dual-ported cache.