A unified architectural tradeoff methodology

Authors:
C.-H. Chen;A. K. Somani
Affiliations:
Department of Electronic Engineering, National Yunlin Institute of Technology, Touliu, Yunlin, R.O.C. on Taiwan;Dept. of EE and Dept. of CSE, University of Washington, Seattle, WA
Venue:
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
Year:
1994

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Abstract

We present a unified approach to assess the trade-off of architecture techniques that affect mean memory access time. The architectural features we consider include cache hit ratio, processor stalling features, line size, memory cycle time, the external data bus width of a processor, pipelined memory system, and read by-passing write buffers. We demonstrate how each of these features can be traded off to achieve the desired performance. The performance of an architecture feature is quantified in terms of cache hit ratio based on the equivalence of mean memory delay time. This paper investigates the implication of architectural tradeoffs on the pin count, memory system design, and on-chip cache area for microprocessor systems.