Quantitative system performance: computer system analysis using queueing network models
Quantitative system performance: computer system analysis using queueing network models
Exact performance estimates for multiprocessor memory and bus interference
IEEE Transactions on Computers
The Balance Multiprocessor System
IEEE Micro
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Modeling and Performance Analysis of Single-Bus Tightly-Coupled Multiprocessors
IEEE Transactions on Computers
Evaluating Design Choices for Shared Bus Multiprocessors in a Throughput-Oriented Environment
IEEE Transactions on Computers
Synthetic Traces for Trace-Driven Simulation of Cache Memories
IEEE Transactions on Computers
A unified architectural tradeoff methodology
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
The SPLASH-2 programs: characterization and methodological considerations
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Architecture Technique Trade-Offs Using Mean Memory Delay Time
IEEE Transactions on Computers
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
ACM Computing Surveys (CSUR)
Complete Computer System Simulation: The SimOS Approach
IEEE Parallel & Distributed Technology: Systems & Technology
A Trace-Driven Simulator for Performance Evaluation of Cache-Based Multiprocessor Systems
IEEE Transactions on Parallel and Distributed Systems
Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Lower Bounds on the Loading of Multiple Bus Networks for Binary Tree Algorithms
IEEE Transactions on Computers
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We present an easy-to-use model that addresses the practical issues in designing bus-based shared-memory multiprocessor systems. The model relates the shared-bus width, bus cycle time, cache memory, the features of a program execution, and the number of processors on a shared bus to a metric called request utilization. The request utilization is treated as the scaling factor for the effective average waiting processors in computing the queuing delay cycles. Simulation study shows that the model performs very well in estimating the shared bus response time. Using the model, a system designer can quickly decide the number of the processors that a shared bus is able to support effectively, the size of the cache memory a system should use, and the bus cycle time that the main memory system should provide. With the model, we show that the design favors caching the requests for a contention-based medium instead of speeding up the transfers although the same performance can be respectively achieved by the two techniques in a contention-free situation.