VLSI assist for a multiprocessor
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
ACM Computing Surveys (CSUR)
ACM Computing Surveys (CSUR)
A survey of commercial parallel processors
ACM SIGARCH Computer Architecture News - Special Issue: Architectural Support for Operating Systems
A sequencing-based taxonomy of I/0 systems and review of historical machines
ACM SIGARCH Computer Architecture News
A multiprocessor configuration in accordance with the aspects of physical and systems design
ACM SIGARCH Computer Architecture News
Delirium: an embedding coordination language
Proceedings of the 1990 ACM/IEEE conference on Supercomputing
Architecture, design, and performance of Application System/400 (AS/400) multiprocessors
IBM Journal of Research and Development
Mapping applications onto a cache coherent multiprocessor
Proceedings of the 1992 ACM/IEEE conference on Supercomputing
ISSAC '94 Proceedings of the international symposium on Symbolic and algebraic computation
An Easy-to-Use Approach for Practical Bus-Based System Design
IEEE Transactions on Computers
A process cache memory for tightly coupled multiprocessor systems
ACM-SE 30 Proceedings of the 30th annual Southeast regional conference
Performance Analysis of Multilevel Bus Networks for Hierarchical Multiprocessors
IEEE Transactions on Computers
Automatic Generation of Self-Scheduling Programs
IEEE Transactions on Parallel and Distributed Systems
Parallel ray tracing on a chip
Practical parallel rendering
Evaluation of cache consistency algorithm performance
MASCOTS '96 Proceedings of the 4th International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems
Pipelined functional tree accesses and updates: scheduling, synchronization, caching and coherence
Journal of Functional Programming
Efficient shared-memory support for parallel graph reduction
Future Generation Computer Systems
Heterogeneous-race-free memory models
Proceedings of the 19th international conference on Architectural support for programming languages and operating systems
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A description is given of the architecture, operating system, and performance of Balance, a shared-memory, tightly coupled multiprocessor system. Balance can contain two to thirty 32-bit microprocessors with an aggregate performance of up to 21 million instructions per second (MIPS). Each processor has a private cache as well as a small local memory to hold frequently used kernel routines. The system features a high-bandwidth pipelined bus, up to 28 Mbytes of main memory, a diagnostic and console processor, up to four IEEE 769 (Multibus) adapters, an IEEE 802.3 (Ethernet) LAN interface, and an ANSI Small Computer System Interface (SCSI). Dynix, a multiprocessor operating system supporting both the 4.2 BSD and System V Unix environments, manages Balance, providing transparent support for multiprocessing as well as tools and libraries for developing parallel applications. The various subsystems and the Dynix operating system are examined. Applications and performance are discussed.