4.2BSD and 4.3BSD as examples of the UNIX system
ACM Computing Surveys (CSUR) - The MIT Press scientific computation series
Cache coherence protocols: evaluation using a multiprocessor simulation model
ACM Transactions on Computer Systems (TOCS)
A class of compatible cache consistency protocols and their support by the IEEE futurebus
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Cache memory optimization to reduce processor/memory traffic
Advances in VLSI and Computer Systems
The Balance Multiprocessor System
IEEE Micro
Firefly: A Multiprocessor Workstation
IEEE Transactions on Computers - Special issue on architectural support for programming languages and operating systems
Implementing a cache consistency protocol
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Experience Using Multiprocessor Systems—A Status Report
ACM Computing Surveys (CSUR)
ACM Computing Surveys (CSUR)
Communications of the ACM
Computer Architecture and Parallel Processing
Computer Architecture and Parallel Processing
Using cache memory to reduce processor-memory traffic
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
A low-overhead coherence solution for multiprocessors with private cache memories
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
An economical solution to the cache coherence problem
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Reduction of memory interference in multiprocessor systems
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
AFIPS '72 (Spring) Proceedings of the May 16-18, 1972, spring joint computer conference
A Trace-Driven Simulator for Performance Evaluation of Cache-Based Multiprocessor Systems
IEEE Transactions on Parallel and Distributed Systems
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Analysis of the simulation outputs and of the behaviour of some prototypes of shared-bus multiprocessors with cache memories showed that: (i) system performance depends on the percentage of write operations operating on shared copies and (ii) some events (such as process migration, execution of input/output interrupt routines on different processors, and so on) create a high number of shared copies derived from memory blocks belonging to private data of processes. Starting from these results, we have designed a new coherence protocol which works to reduce the number of shared copies. The basic new idea lies in (i) identifying the copies unused by the running process and (ii) destroying them when they are involved in shared-bus transactions. This paper describes this idea, the coherence protocol, the cache architecture requirements needed to realize such an idea.