Quantitative system performance: computer system analysis using queueing network models
Quantitative system performance: computer system analysis using queueing network models
Cache coherence protocols: evaluation using a multiprocessor simulation model
ACM Transactions on Computer Systems (TOCS)
Cache memory optimization to reduce processor/memory traffic
Advances in VLSI and Computer Systems
Firefly: A Multiprocessor Workstation
IEEE Transactions on Computers - Special issue on architectural support for programming languages and operating systems
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
IEEE Transactions on Computers
Analysis and Comparison of Cache Coherence Protocols for a Packet-Switched Multiprocessor
IEEE Transactions on Computers
Synthetic Traces for Trace-Driven Simulation of Cache Memories
IEEE Transactions on Computers
Implementing a cache consistency protocol
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
ACM Computing Surveys (CSUR)
Cold-start vs. warm-start miss ratios
Communications of the ACM
The working set model for program behavior
Communications of the ACM
A process cache memory for tightly coupled multiprocessor systems
ACM-SE 30 Proceedings of the 30th annual Southeast regional conference
Analysis of Cache Performance for Operating Systems and Multiprogramming
Analysis of Cache Performance for Operating Systems and Multiprogramming
Program Behavior: Models and Measurements
Program Behavior: Models and Measurements
The Cache-Coherence Problem in Shared-Memory Multiprocessors: Hardware Solutions
The Cache-Coherence Problem in Shared-Memory Multiprocessors: Hardware Solutions
Using Processor-Cache Affinity Information in Shared-Memory Multiprocessor Scheduling
IEEE Transactions on Parallel and Distributed Systems
Using cache memory to reduce processor-memory traffic
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
Reducing coherence-related overhead in multiprocessor systems
PDP '95 Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing
Estimating Performance of Single Bus, Shared Memory Multiprocessors
Estimating Performance of Single Bus, Shared Memory Multiprocessors
Simulation analysis of data-sharing in shared memory multiprocessors
Simulation analysis of data-sharing in shared memory multiprocessors
IEEE Transactions on Parallel and Distributed Systems
An Easy-to-Use Approach for Practical Bus-Based System Design
IEEE Transactions on Computers
Performance-steered design of software architectures for embedded multicore systems
Software—Practice & Experience
Trace Factory: Generating Workloads for Trace-Driven Simulation of Shared-Bus Multiprocessors
IEEE Parallel & Distributed Technology: Systems & Technology
The ChARM Tool for Tuning Embedded Systems
IEEE Micro
On cache memory hierarchy for Chip-Multiprocessor
ACM SIGARCH Computer Architecture News
Fine-grain design space exploration for a cartographic SoC multiprocessor
ACM SIGARCH Computer Architecture News
RSP '97 Proceedings of the 8th International Workshop on Rapid System Prototyping (RSP '97) Shortening the Path from Specification to Prototype
Journal of Parallel and Distributed Computing
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Speeding-up multiprocessors running DBMS workloads through coherence protocols
International Journal of High Performance Computing and Networking
A modeling method by eliminating execution traces for performance evaluation
Proceedings of the Conference on Design, Automation and Test in Europe
A model-based method for evaluating embedded system performance by abstraction of execution traces
ECMFA'10 Proceedings of the 6th European conference on Modelling Foundations and Applications
ARCS'10 Proceedings of the 23rd international conference on Architecture of Computing Systems
Mesoscale performance simulation of multicore processor systems
Software and Systems Modeling (SoSyM)
| Hi-index | 0.00 |
We describe a simulator which emulates the activity of a shared memory, common bus multiprocessor system with private caches. Both kernel and user program activities are considered, thus allowing an accurate analysis and evaluation of coherence protocol performance. The simulator can generate synthetic traces, based on a wide set of input parameters which specify processor, kernel and workload features. Other parameters allow us to detail the multiprocessor architecture for which the analysis has to be carried out. An actual-trace-driven simulation is possible, too, in order to evaluate the performance of a specific multiprocessor with respect to a given workload, if traces concerning this workload are available. In a separate section, we describe how actual traces can also be used to extract a set of input parameters for synthetic trace generation. Finally, we show how the simulator may be successfully employed to carry out a detailed performance analysis of a specific coherence protocol.