Performance prediction and tuning on a multiprocessor
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Models of Access Delays in Multiprocessor Memories
IEEE Transactions on Parallel and Distributed Systems
A Trace-Driven Simulator for Performance Evaluation of Cache-Based Multiprocessor Systems
IEEE Transactions on Parallel and Distributed Systems
Computer Performance Evaluation Methodology
IEEE Transactions on Computers
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This paper presents the methodology used and the results obtained in studying design trade-offs for the PowerPC family of processors and system designs using these processors. Specifically, the effects of various cache hierarchies and multiprocessor designs on system performance are examined. Issues dealt with include the performance speedup for different multi-processor configurations and memory subsystem designs when executing various workloads. Four generic types of workloads were studied. They are defined such that most actual applications should fit into one of the four categories. Results obtained show that system performance is sensitive to the access distance of L2 and L3 caches for many cache sizes and workloads. Required versus available bus bandwidth was examined and found to not be a problem for the systems and workloads under consideration.